Engagement Overview
Pintail Technologies is a leading software developer for semiconductor testers, with offices in Plano and Austin. Their flagship software suite includes offline engineering diagnostic tools and a real-time online adaptive control engine.
From September to December 2007, Pulse Meridian engaged with Pintail Technologies to provide statistical modeling and optimization consulting. Our team collaborated with Pintail's engineers to research, develop and prototype a next-generation analysis tool to improve yield through modeling the relationship between physical wafer diagnostics and functional chip tests.
Background
Businesses that design the integrated circuits that control devices such as cell phones, digital cameras and mp3 players rely upon semiconductor fabrication plants to implement their designs. Many of these companies are fabless, meaning that they do not operate the plant themselves. Instead, the fabrication is carried out by third party fabs, in remote sites.
Design companies want their fabs to create functioning chips while expending minimal resources. The key to minimizing cost is maximizing yield. Yield is the percentage of fabricated chips that function according to the design specification. Delicate tuning of the fabrication process can reduce defects in the manufactured chips, increasing the chance that they perform to specification.
The fabs are required to ensure that the physical characteristics of the silicon wafers they produce fall within specified parameters. Along with the thousands individual chips laid out on the silicon, fabs place 7 or so test sites throughout the wafer. After fabrication, a wafer is subjected to Process Control Monitoring (PCM), which performs 20 or so tests on these sites.
Wafers that pass PCM are shipped to testing facilities where they are sliced into individual chips and tested. One by one, the chips are fed into large machines that carry out upwards of 14,000 parametric tests to determine if they perform to specification. If a chip fails any one of these parametric tests by producing outputs outside of the tolerable limits, it is considered defective and is discarded.
Semiconductor companies are aware that there is a relationship between the 14,000 or so parametric outputs of a chip and the 20 or so PCM outputs of the wafer from which it came. However, modeling this relationship is difficult because it is non-linear and available data often spans only a small subspace of high-dimensional input space.
Results
Our team divided the project into two stages: modeling and optimization. Our approach to modeling included dimensionality reduction and several varieties of regression over the distribution parameters of the test outputs. We began with a simple linear model verified on contrived data, then after building up the infrastructure to process the massive physical testing data sets, expanded the model to include higher order interactions.
After completing the initial model, we developed an optimization framework to compare models based on predicted yield. We explored several gradient and non-gradient optimization algorithms from the literature. Preliminary results indicate that one should be able to use our model to find PCM settings that will lead to higher yields.
The project had two main deliverables. First, we delivered prototype code to extract data from Pintail's data warehouse, construct a statistical model, optimize it, and recommend PCM settings along with predicted yield. And second, we provided a detailed white paper describing the mathematics and implementation details of our prototype, as well as a summary of experiments demonstrating the promise of our approach. With these in hand, Pintail became empowered to move forward with a production-ready system.